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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad8110/ad8111 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 260 mhz, 16 8 buffered video crosspoint switches features 16 8 high-speed nonblocking switch arrays ad8110: g = +1 ad8111: g = +2 serial or parallel switch array control serial data out allows daisy chaining of multiple crosspoints to create larger switch arrays pin-compatible with ad8108/ad8109 8 8 switch arrays for a 16 16 array see ad8116 complete solution buffered inputs eight output amplifiers, ad8110 (g = +1), ad8111 (g = +2) drives 150 v loads excellent video performance 60 mhz 0.1 db gain flatness 0.02% differential gain error (r l = 150 v) 0.028 differential phase error (r l = 150 v) excellent ac performance 260 mhz C3 db bandwidth 500 v/ms slew rate low power of 50 ma low all hostile crosstalk of C78 db @ 5 mhz output disable allows direct connection of multiple device outputs reset pin allows disabling of all outputs (connected through a capacitor to ground provides power- on reset capability) excellent esd rating: exceeds 4000 v human body model 80-lead lqfp package (12 mm 12 mm) applications routing of high-speed signals including: composite video (ntsc, pal, s, secam) component video (yuv, rgb) compressed video (mpeg, wavelet) 3-level digital video (hdb3) functional block diagram ad8110/ad8111 switch matrix output buffer g = +1, g = +2 40 40 128 40-bit shift register with 5-bit parallel loading parallel latch decode 8 5:16 decoders 8 clk data in update ce reset 16 inputs a0 data out 8 outputs set individual or reset all outputs to "off" a1 a2 ser/par d0 d1 d2 d3 enable/disable d4 product description the ad8110 and ad8111 are high-speed 16 8 video cross- point switch matrices. they offer a ? db signal band width greater than 260 mhz, and channel switch times of less than 25 ns with 1% settling. with ?8 db of crosstalk and ?7 db isolation (@ 5 mhz), the ad8110/ad8111 are useful in many high-speed applications. the differential gain and differential phase of better than 0.02% and 0.02 respectively, along with 0.1 db flatness out to 60 mhz, make the ad8110/ad8111 ideal for video signal switching. the ad8110 and ad8111 include eight independent output buffers that can be placed into a high impedance state for paral- leling crosspoint outputs so that off channels do not load the output bus. the ad8110 has a gain of +1, while the ad 8111 offers a gain of +2. they operate on voltage supplies of 5 v while consuming only 50 ma of idle current. the channel switching is performed via a serial digital control (which can accommodate ?aisy chaining?of several devices) or via a parallel control, allowing updating of an individual output without repro- gramming the entire array. the ad8110/ad8111 is packaged in an 80-lead lqfp package and is available over the extended industrial temperature range of ?0 c to +85 c.
rev. a C2C ad8110/ad8111?pecifications (v s = 5 v, t a = +25 c, r l = 1 k unless otherwise noted.) ad8110/ad8111 parameter conditions min typ max unit reference dynamic performance ? db bandwidth 200 mv p-p, r l = 150 ? 300/190 390/260 mhz tpc 1, 7 2 v p-p, r l = 150 ? 150 mhz tpc 1, 7 propagation delay 2 v p-p, r l = 150 ? 5ns slew rate 2 v step, r l = 150 ? 500 v/ s settling time 0.1%, 2 v step, r l = 150 ? 40 ns tpc 6, 12 gain flatness 0.05 db, 200 mv p-p, r l = 150 ? 60/40 mhz tpc 1, 7 0.05 db, 2 v p-p, r l = 150 ? 65/40 mhz tpc 1, 7 0.1 db, 200 mv p-p, r l = 150 ? 80/57 mhz tpc 1, 7 0.1 db, 2 v p-p, r l = 150 ? 70/57 mhz tpc 1, 7 noise/distortion performance differential gain error ntsc or pal, r l = 1 k ? 0.01 % ntsc or pal, r l =150 ? 0.02 % differential phase error ntsc or pal, r l = 1 k ? 0.01 degrees ntsc or pal, r l = 150 ? 0.02 degrees crosstalk, all hostile f = 5 mhz 78/85 db tpc 2, 8 f = 10 mhz 70/80 db tpc 2, 8 off isolation, input-output f = 10 mhz, r l =150 ? , one channel 93/99 db tpc 17, 23 input voltage noise 0.01 mhz to 50 mhz 15 nv/ hz tpc 14, 20 dc performance gain error r l = 1 k ? 0.04/0.1 0.07/0.5 % r l = 150 ? 0.15/0.25 % gain matching no load, channel-channel 0.02/1.0 % r l = 1 k ? , channel-channel 0.09/1.0 % gain temperature coefficient 0.5/8 ppm/ c output characteristics output impedance dc, enabled 0.2 ? 18, 24 disabled 10/0.001 m ? 15, 21 output disable capacitance disabled 2 pf output leakage current disabled, ad8110 only 1/na a output voltage range no load 2.5 3v output current 20 40 ma short circuit current 65 ma input characteristics input offset voltage worst case (all configurations) 5 20 mv 29, 35 temperature coefficient 12 v/ c 30, 36 input voltage range 2.5/ 1.25 3/ 1.5 v input capacitance any switch configuration 2.5 pf input resistance 1 10 m ? input bias current per output selected 2 5 a switching characteristics enable on time 60 ns switching time, 2 v step 50% update to 1% settling 25 ns switching transient (glitch) measured at output 20/30 mv p-p 16, 22 power supplies supply current avcc, outputs enabled, no load 38 ma avcc, outputs disabled 15 ma avee, outputs enabled, no load 38 ma avee, outputs disabled 15 ma dvcc 11 ma supply voltage range 4.5 to 5.5 v psrr f = 100 khz 75/78 db 13, 19 f = 1 mhz ?5/?8 db operating temperature range temperature range operating (still air) ?0 to +85 c ja operating (still air) 48 c/w specifications subject to change without notice.
rev. a ad8110/ad8111 C3C timing characteristics (serial) limit parameter symbol min typ max unit serial data setup time t 1 20 ns clk pulsewidth t 2 100 ns serial data hold time t 3 20 ns clk pulse separation, serial mode t 4 100 ns clk to update update update d update reset update figure 1. timing diagram, serial mode table i. logic levels v ih v il v oh v ol i ih i il i oh i ol reset ser reset ser reset ser reset ser ce update ce update ce update ce update d d d
rev. a ad8110/ad8111 C4C timing characteristics (parallel) limit parameter symbol min max unit data setup time t 1 20 ns clk pulsewidth t 2 100 ns data hold time t 3 20 ns clk pulse separation t 4 100 ns clk to update update update update reset update figure 2. timing diagram, parallel mode table ii. logic levels v ih v il v oh v ol i ih i il i oh i ol reset ser reset ser reset ser reset ser ce update ce update ce update ce update d d d
rev. a ad8110/ad8111 C5C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8110/ad8111 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.0 v internal power dissipation 2 ad8110/ad8111 80-lead plastic lqfp (st) . . . . . 2.6 w input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s output short circuit duration . . . . . . . . . . . . . . . . . . . . . observe power derating curves storage temperature range . . . . . . . . . . . . ?5 c to +125 c lead temperature range (soldering 10 sec) . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air (t a = 25 c): 80-lead plastic lqfp (st): ja = 48 c/w. maximum power dissipation the maximum power that can be safely dissipated by the ad8110/ad8111 is limited by the associated rise in junction temperature. the maximum safe junction tem perature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150 c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175 c for an extended period can result in device failure. while the ad8110/ad8111 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150 c) is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves shown in figure 3. ambient temperature ? c 5.0 maximum power dissipation ?watts 4.0 0 ?0 80 ?0 ?0 ?0 ?0 0 10 20 30 40 50 60 70 3.0 2.0 1.0 t j = 150 c 90 figure 3. maximum power dissipation vs. temperature ordering guide temperature package package model range description option ad8110ast ?0 c to +85 c 80-lead plastic lqfp (12 mm 12 mm) st-80a ad8111ast ?0 c to +85 c 80-lead plastic lqfp (12 mm 12 mm) st-80a ad8110-eb evaluation board ad8111-eb evaluation board
rev. a ad8110/ad8111 C6C table iii. operation truth table ser ce update clk data in data out reset par operation/comment 1 x x x x x x no change in logic. 01 f f d clk q 3 to 8 decoder a0 a1 a2 clk ce update 8 128 data in (serial) (output enable) ser /par reset (output enable) out0 en data out parallel data d q clk d q clk d q clk d q clk d1 d2 d3 d q clk d q clk d q clk d q clk d q clk out1 en out2 en out3 en out4 en out5 en out6 en out7 en d le q clr out7 en output enable switch matrix s d1 q d0 d0 s d1 q d0 s d1 q d0 s d1 q d0 s d1 q d0 s d1 q d0 s d1 q d0 s d1 q d0 d q clk s d1 q d0 d4 decode d le q clr out0 en d le out0 b0 q d le q out0 b1 d le q out0 b2 d le q out0 b3 d le out1 b0 q d le q clr out6 en d le out7 b0 q d le out7 b1 q d le out7 b2 q d q clk s d1 q d0 s d1 q d0 d le out7 b3 q s d1 q d0 figure 4. logic diagram
rev. a ad8110/ad8111 C7C pin function descriptions pin name pin numbers pin description inxx 66, 68, 70, 72, 74, 76, 78, analog inputs; xx = channel numbers 00 through 15. 1, 3, 5, 7, 9, 11, 13, 15, 64 data in 57 serial data input, ttl compatible. clk 58 clock, ttl compatible. falling edge triggered. data out 59 serial data out, ttl compatible. update reset ce must be ?ow?to clock in and latch data. ser / par 55 selects serial data mode, ?ow?or parallel data mode, ?igh.? must be connected. outyy 41, 38, 35, 32, 29, 26, 23, 20 analog outputs yy = channel numbers 00 through 07. agnd 2, 4, 6, 8, 10, 12, 14, 16, 46 analog ground for inputs and switch matrix. 65, 67, 69, 71, 73, 75, 77 dvcc 63, 79 5 v for digital circuitry. dgnd 62, 80 ground for digital circuitry. avee 17, 45 ? v for inputs and switch matrix. avcc 18, 44 +5 v for inputs and switch matrix. agndxx 42, 39, 36, 33, 30, 27, 24, 21 gr ound for output amp, xx = output channel numbers 00 through 07. must be connected. avccxx/yy 43, 37, 31, 25, 22, 19 +5 v for out put amplifier that is shared by channel numbers xx and yy. must be connected. aveexx/yy 40, 34, 28, 22 ? v for output amplifier that is shared by channel numbers xx and yy. must be connected. a0 54 parallel data input, ttl compatible (output select lsb). a1 53 parallel data input, ttl compatible (output select). a2 52 parallel data input, ttl compatible (output select msb). d0 51 parallel data input, ttl compatible (input select lsb). d1 50 parallel data input, ttl compatible (input select). d2 49 parallel data input, ttl compatible (input select). d3 48 parallel data input, ttl compatible (input select msb). d4 47 parallel data input, ttl compatible (output enable). esd esd input v cc av ee esd esd output v cc av ee 1k (ad8111 only) esd esd reset v cc 20k dgnd esd esd input v cc dgnd esd esd output v cc 2k dgnd figure 5. i/o schematics a. analog input b. analog output c. reset input d. logic input e. logic output
rev. a ad8110/ad8111 C8C pin configuration 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 56 57 58 59 54 55 52 53 50 51 60 45 46 47 48 43 44 42 49 41 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 12 pin 1 identifier top view (pins down) 0.5mm lead pitch ad8110/ad8111 16 8 80l lqfp (12mm 12mm) 40 39 38 37 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 36 dgnd dvcc in07 agnd in06 agnd in05 agnd in04 agnd in03 agnd in02 agnd in01 agnd in00 dvcc dgnd reset agnd07 avee06/07 out06 agnd06 avcc05/06 out05 agnd05 avee04/05 out04 agnd04 avcc03/04 out03 agnd03 avee02/03 out02 agnd02 avcc01/02 out01 agnd01 ce data out clk data in update ser /par a0 a1 a2 d0 d1 d2 d3 d4 agnd avee avcc avcc00 agnd00 out00 in08 agnd in09 agnd in10 agnd in11 agnd in12 agnd in13 agnd in14 agnd in15 agnd avee avcc avcc07 out07 avee00/01
rev. a C9C typical performance characteristics ad8110/ad8111 frequency e hz gain e db e 2 1 0 e 1 e 3 100k 1m 1g 10m 100m flatness e db 0.2 0.1 0 e 0.1 e 0.2 e 0.3 gain flatness 2 3 0.3 4 5 200mv p-p 2v p-p r l = 150 tpc 1. ad8110 frequency response frequency e mhz crosstalk e db e 30 e 40 e 100 0.3 1 200 10 100 e 50 e 60 e 70 e 80 e 90 adjacent all hostile r l = 1k tpc 2. ad8110 crosstalk vs. frequency frequency e hz distortion e db 100k 1m 100m 10m e 100 e 40 e 50 e 60 e 70 e 80 e 90 2nd harmonic 3rd harmonic r l = 150 v out = 2v p-p tpc 3. ad8110 distortion vs. frequency 50 25 0 25 50 25ns/div 25mv/div r l = 150 tpc 4. ad8110 step response, 100 mv step 1 0.5 0 0.5 1 25ns/div 0.5v/div r l = 150 tpc 5. ad8110 step response, 2 v step 2v step r l = 150 0 10 20304050607080 10ns/div 0.1%/div tpc 6. ad8110 settling time
rev. a ad8110/ad8111 C10C frequency e hz gain e db e 2 1 0 e 1 e 3 100k 1m 1g 10m 100m flatness e db 0.4 0.2 0 e 0.2 e 0.4 2 3 0.6 gain flatness e 0.6 0.8 200mv p-p 2v p-p e 0.8 4 5 tpc 7. ad8111 frequency response frequency e mhz crosstalk e db e 20 e 30 e 90 0.3 1 200 10 100 e 40 e 50 e 60 e 70 e 80 e 100 e 110 r l = 1k adjacent all hostile tpc 8. ad8111 crosstalk vs. frequency frequency hz distortion db 30 40 100 100k 1m 100m 10m 50 60 70 80 90 2nd harmonic 3rd harmonic r l = 150 v out = 2v p-p tpc 9. ad8111 distortion vs. frequency 50 25 0 25 50 25ns/div 25mv/div tpc 10. ad8111 step response, 100 mv step 1 0.5 0 0.5 1 25ns/div 500mv/div tpc 11. ad8111 step response, 2 v step 2v step rto r l = 150 0 10 20304050607080 10ns/div 0.1%/div tpc 12. ad8111 settling time
rev. a ad8110/ad8111 C11C frequency hz power supply rejection db 30 40 10k 100k 10m 1m 50 60 70 80 90 r l = 150 tpc 13. ad8110 psrr vs. frequency frequency hz 100 56.3 10 1k 10m 100k 31.6 17. 8 10 5.63 3.16 100 10k 1m nv/ hz tpc 14. ad8110 voltage noise vs. frequency frequency mhz output impedance 1m 0.1 1 500 10 100k 10k 1k 100 100 tpc 15. ad8110 output impedance, disabled update input typical video out (rto) 5 4 3 2 1 0 10 e 10 0 50ns/div 10mv/div 1v/div switching between two inputs tpc 16. ad8110 switching transient (glitch) frequency hz off isolation e db 100k 1m 500m 10m 100m v in = 2v p-p r l = 150 50 e 60 e 70 e 80 e 90 e 100 e 110 e 120 e 130 '+5&0 3&&62 <2 10,000 1000 100 10 1 0.1 frequency hz output impedance e 100k 1m 500m 10m 100m '+5&3 3&&62
rev. a ad8110/ad8111 C12C frequency hz power supply rejection e db rti 10k 100k 1m 10m e 30 e 40 e 50 e 60 e 70 e 80 r l = 150 tpc 19. ad8111 psrr vs. frequency frequency hz 100 56.3 10 1k 10m 100k 31.6 17.8 10 5.63 3.16 100 10k 1m nv/ hz tpc 20. ad8111 voltage noise vs. frequency frequency mhz output impedance 100k 0.1 1 500 10 10k 1k 100 10 100 tpc 21. ad8111 output impedance, disabled 1v/div update input typical video out (rto) 10mv/div 5 4 3 2 1 0 10 0 e 10 50ns/div switching between two inputs tpc 22. ad8111 switching transient (glitch) frequency hz off isolation e db 100k 1m 500m 10m 100m e 60 e 80 e 100 e 120 e 130 e 110 e 90 e 70 e 50 v out = 2v p-p r l = 150 40 ` tpc 23. ad8111 off isolation, input-output frequency hz output impedance 1k 100k 1m 500m 10m 100 10 1 0.1 100m tpc 24. ad8111 output impedance, enabled
rev. a ad8110/ad8111 C13C input impedance e 1m 100k 10k 1k 100 10m 30k 100k 1m 10m 100m 500m frequency e hz tpc 25. ad8110 input impedance vs. frequency frequency e hz gain e db 14 12 e 4 0.1m 1m 10m 100m 1g 10 8 0 6 4 2 e 2 18pf = 7.7db 12pf = 4.5db 3g v in = 200mv p-p r l = 150 tpc 26. ad8110 f requency response vs. capacitive load frequency e hz flatness e db 0.7 0.6 e 0.2 0.1m 1m 10m 100m 1g 0.5 0.4 0 0.3 0.2 0.1 e 0.1 v in = 200mv p-p r l = 150 c l = 18pf c l = 12pf 3g tpc 27. ad8110 flatness vs. capacitive load v out update input 1 at +1v input 0 at e 1v 1 0 e 1 5 0 50ns/div 2v/div 1v/div tpc 28. ad8110 switching time offset voltage e volts frequency 260 60 e 0.020 e 0.010 0.000 0.010 240 180 160 120 80 220 200 140 100 40 20 0 0.020 '+5#4 3&&62
temperature e c v os e mv 2.0 e 2.0 e 60 e 40 100 e 20 0 20 40 60 80 1.5 0 e 0.5 e 1.0 e 1.5 1.0 0.5 tpc 30. ad8110 offset voltage vs. temperature (normalized at 25 e c)
rev. a ad8110/ad8111 C14C frequency hz input impedance e 30k 1m 500m 10m 100m 1m 100k 10k 1k 100 100k 10m tpc 31. ad8111 input impedance vs. frequency gain e db 12 10 e 6 8 6 e 2 4 2 0 e 4 frequency e hz 0.1m 1m 10m 100m 1g 3g 18pf 12pf tpc 32. ad8111 f requency response vs. capacitive load gain e db 0.7 0.6 e 0.1 0.5 0.4 0 0.3 0.2 0.1 e 0.2 e 0.3 frequency e hz 0.1m 1m 10m 100m 1g 3g 12pf 18pf v in = 100mv r l = 150 tpc 33. ad8111 flatness vs. capacitive load v out update input 1 at +1v input 0 at e 1v 1 0 e 1 5 0 50ns/div 2v/div 1v/div tpc 34. ad8111 switching time offset voltage e volts frequency 120 480 360 320 240 160 440 400 280 200 80 40 0 e 0.020 0.020 e 0.010 0.000 0.010 tpc 35. ad8111 offset voltage distribution (rti) temperature e c v os e mv 2.0 e 2.0 e 60 e 40 100 e 20 0 20 40 60 80 1.5 0 e 0.5 e 1.0 e 1.5 1.0 0.5 tpc 36. ad8111 offset voltage drift vs. temperature (normalized at 25 e c)
rev. a ad8110/ad8111 C15C theory of operation the ad8110 (g = +1) and ad8111 (g = +2) share a common core architecture consisting of an array of 128 transconductance (gm) input stages organized as eight 16:1 multiplexers with a common, 16-line analog input bus. each multiplexer is basically a folded-cascode high-speed voltage feedback amplifier with 16 input stages. the input stages are npn differential pairs whose differential current outputs are combined at the output stage, which contains the high impedance node, compensation and a complementary emitter follower output buffer. in the ad8110, the output of each multiplexer is fed directly back to the inverting inputs of its 16 gm stages. in the ad8111, the feedback network is a voltage divider consisting of two equal resistors. this switched-gm architecture results in a low power crosspoint switch that is able to directly drive a back terminated video load (150 ) with low distortion (differential gain and differential phase errors are better than 0.02% and 0.02 , respectively). this design also achieves high input resistance and low input ca paci- tance without the signal degradation and power dissipation of additional input buffers. however, the small input bias current at any input will increase almost linearly with the number of out- puts programmed to that input. the output disable feature of these crosspoints allows larger switch matrices to be built simply by busing together the outputs of multiple 16 8 ics. however, while the disabled output im ped- ance of the ad8110 is very high (10 m ), that of the ad8111 is limited by the resistive feedback network (which has a nominal total resistance of 1 k ) that appears in parallel with the disabled output. if the outputs of multiple ad8111s are connected th rough separate back termination resistors, the loading due to these finite output impedances will lower the effective back termination impedance of the overall matrix. this problem is eliminated if the outputs of multiple ad8111s are connected directly and share a single back termination resistor for each output of the overall matrix. this configuration increases the capacitive loading of the disabled ad8111 on the output of the enabled ad8111. applications the ad8110/ad8111 have two options for changing the programming of the crosspoint matrix. in the first option, a serial word of 40 bits can be provided that will update the entire matrix each time. the second option allows for changing a single outputs programming via a parallel interface. the serial option requires fewer signals, but requires more time (clock cycles) for changing the programming, while the parallel programming tech- nique re quires m ore signals, but can change a single output at a time and re quires fewer clock cycles to complete programming. serial programming the serial programming mode uses the device pins ce update ser ser ce ce update update update update update ce ce update ser parallel programming when using the parallel programming mode, it is not necessary to reprogram the entire device when making changes to the matrix. in fact, parallel programming allows the modification of a single output at a time. since this takes only one clk/ update reset does not reset all registers in the ad8110/ ad8111. when taken low, the reset reset all outputs be programmed to a desired state after power-up.
rev. a ad8110/ad8111 C16C nnnnnnnnnn n6nnn5nnnnn nnnnnnnnn6 nnn5nnn ce update do not apply low logic levels to both ce and update after power is initially applied. programming the full shift register one time to a desired state by either serial or parallel programming after initial power-up will eliminate the possibility of program- ming the matrix to an unknown state. to change an output? programming via parallel programming, ser update ce update update update power-on reset when powering up the ad8110/ad8111 it is usually desirable to have the outputs come up in the disabled state. the reset reset does not reset all registers in the ad8110/ad8111. this is important when operating in the parallel programming mode. please refer to that section for information about programming internal registers after power- up. serial programming will program the entire matrix each time, so no special considerations apply. since the data in the shift register is random after power-up, it should not be used to program the matrix or else the matrix can enter unknown states. to prevent this, do not apply logic low signals to both ce and update initially after power-up. the shift register should first be loaded with the desired data, and then update reset p reset reset gain selection the 16 8 crosspoints come in two versions depending on the desired gain of the analog circuit paths. the ad8110 device is unity gain and can be used for analog logic switching and other applications where unity gain is desired. the ad8110 can also be used for the input and interior sections of larger crosspoint arrays where termination of output signals is not usually used. the ad8110 outputs have a very high impedance when their outputs are disabled. for devices that will be used to drive a terminated cable with its outputs, the ad8111 can be used. this device has a built-in gain of two that eliminates the need for a gain-of-two buffer to drive a video line. because of the presence of the feedback network in these devices, the disabled output impedance is about 1 k . if external amplifiers are used to provide a gain = +2, analog devices ad8079 provides a fixed g = +2 function. creating larger crosspoint arrays the ad8110/ad8111 are high-density building blocks for creating crosspoint arrays of dimensions larger than 16 8. various features such as output disable, chip enable, and gain- of-one- and-two options are useful for creating larger arrays. for very large arrays, they can be used along with the ad8116, a 16 16 video crosspoint device. in addition, when required for customizing a crosspoint array size, they can be used with the ad8108 and ad8109, a pair (unity gain and gain-of-two) of 8 8 video crosspoint switches. the first consideration in constructing a larger crosspoint is to determine the minimum number of devices that are required. the 16 8 architecture of the ad8110/ad8111 contains 128 points, which is a factor of 32 greater than a 4 1 crosspoint. the pc board area and power consumption savings are readily apparent when compared to using these smaller devices. for a nonblocking crosspoint, the number of points required is the product of the number of inputs multiplied by the number of outputs. nonblocking requires that the programming of a given input to one or more outputs does not restrict the avail- ability of that input to be a source for any other outputs. some nonblocking crosspoint architectures will require more than this minimum as calculated above. also, there are blocking architectures that can be constructed with fewer devices than this minimum. these systems have connectivity available on a statistical basis that is determined when designing the overall system.
rev. a ad8110/ad8111 C17C nnnnnnnnn nnnnnnnnn xnnnnnnn6n nnnnnnnnn nnn6nn0nnnnnn8on r nk n 6 ad8110 or ad8111 16 16 r term in 00 e 15 ad8110 or ad8111 16 16 r term in 16 e 31 8 8 figure 6. a 32 r 8 crosspoint array using two ad8110s or two ad8111s nnnnnnnnnn8on nnnnnn6nn nxnnn6nnnnnnn nnnnnnnnn6nn nnnnnnnn n6 nn5nnnnnnnxn nnnnn6nnnn nnnnnn6nnnn nnnnnnk//7nnk///6n nnnnnk//7nnnn nnnk///5nnnnnnnn nnnnnnn6nn 5nn/okn r nk nnnnnnk//7lk///6n nnn/oknnnnnn nnnnxnnnnn6 nnnnnnnnn nnnnnnxn6nnq nnnnnnnnnk//7n nk///nnnn5n xx5n/okn r nk nnnnxnnnnn n6nnnnnk//75nnnn nnnnnk///6 5nnnnnnnnnn nnonk///5nnn/okn r n/0nnn n6nn5n5nnnnnx 6nnnnnnnnn nnnnnnnn 6nn5nnnnnn nnnnnn6nn5nn nnnnnnnn n6 16 r term in 00 e 15 4 4 in 16 e 31 in 32 e 47 in 48 e 63 in 64 e 79 in 80 e 95 in 96 e 111 in 112 e 127 4 4 4 4 rank 2 16:8 nonblocking (16:16 blocking) rank 1 (8 x ad8110) 128:16 16 r term 4 4 16 r term 4 4 16 r term 4 4 16 r term 4 4 16 r term 4 4 16 r term 4 4 16 r term 4 4 ad8111 ad8110 ad8110 ad8110 ad8110 ad8110 ad8110 ad8110 ad8110 4 1k 4 1k 4 1k 4 1k ad8111 out 00 e 07 nonblocking additional 8 outputs (subject to blocking) figure 7. a gain-of-two 128 r 8 nonblocking crosspoint array (128 r 16 blocking)
rev. a ad8110/ad8111 C18C multichannel video the excellent video specifications of the ad8110/ad8111 make them ideal candidates for creating composite video cross point switches. these can be made quite dense by taking advantage of the ad8110/ad8111s high level of integration and the fact that composite video requires only one crosspoint channel per system video channel. there are, however, other video formats that can be routed with the ad8110/ad8111 requiring more than one crosspoint channel per video channel. some systems use twisted-pair wiring to carry video signals. these systems utilize differential signals and can lower costs because they use lower cost cables, connectors and termination methods. they also have the ability to lower crosstalk and reject common-mode signals, which can be important for equip ment that operates in noisy environments or where common-mode volt- ages are present between transmitting and receiving equipment. in such systems, the video signals are differential; there is a positive and negative (or inverted) version of the signals. these complementary signals are transmitted onto each of the two wires of the twisted pair, yielding a first order zero common- mode signal. at the receive end, the signals are differentially received and converted back into a single-ended signal. when switching these differential signals, two channels are required in the switching element to handle the two differential signals that make up the video channel. thus, one differential video channel is assigned to a pair of crosspoint channels, both input and output. for a single ad8110/ad8111, eight differen- tial video channels can be assigned to the 16 inputs and four to the outputs. this will effectively form an 8 4 differential cross- point switch. programming such a device will require that inputs and outputs be programmed in pairs. this information can be deduced by inspection of the programming format of the ad8110/ad8111 and the requirements of the system. there are other analog video formats requiring more than one analog circuit per video channel. one two-circuit format that is commonly being used in systems such as satellite tv, digital cable boxes and higher quality vcrs, is called s-video or y/c video. this format carries the brightness (luminance or y) portion of the video signal on one channel and the color (chromi- nance, chroma or c) on a second channel. since s-video also uses two separate circuits for one video chan- nel, creating a crosspoint system requires assigning one video channel to two crosspoint channels as in the case of a differential video system. aside from the nature of the video format, other aspects of these two systems will be the same. there are yet other video formats using three channels to carry the video information. video cameras produce rgb (red, green, blue) directly from the image sensors. rgb is also the usual format used by computers internally for graphics. rgb can also be converted to y, r-y, b-y format, sometimes called yuv format. these three-circuit, video standards are referred to as component analog video. the component video standards require three crosspoint chan- nels per video channel to handle the switching function. in a fashion similar to the two-circuit video formats, the inputs and outputs are assigned in groups of three and the appropriate logic programming is performed to route the video signals. crosstalk many systems, such as broadcast video, that handle numerous analog signal channels have strict requirements for keeping the various signals from influencing any of the others in the system. crosstalk is the term used to describe the coupling of the signals of other nearby channels to a given channel. when there are many signals in proximity in a system, as will undoubtedly be the case in a system that uses the ad8110/ ad8111, the crosstalk issues can be quite complex. a good understanding of the nature of crosstalk and some definition of terms is required in order to specify a system that uses one or more ad8110/ad8111s. types of crosstalk crosstalk can be propagated by means of any of three meth- ods. these fall into the categories of electric field, magnetic field and sharing of common impedances. this section will explain these effects. every conductor can be both a radiator of electric fields and a receiver of electric fields. the electric field crosstalk mechanism occurs when the electric field created by the transmitter propa- gates across a stray capacitance (e.g., free space) and couples with the receiver and induces a voltage. this voltage is an unwanted crosstalk signal in any channel that receives it. currents flowing in conductors create magnetic fields that circulate around the currents. these magnetic fields will then generate voltages in any other conductors whose paths they link. the undes- ired induced voltages in these other channels are crosstalk signals. the channels that crosstalk can be said to have a mutual inductance that couples signals from one channel to another. the power supplies, grounds and other signal return paths of a multichannel system are generally shared by the various chan- nels. when a current from one channel flows in one of these paths, a voltage that is developed across the impedance becomes an input crosstalk signal for other channels that share the com- mon impedance. all these sources of crosstalk are vector quantities, so the magnitudes cannot be simply added together to obtain the total crosstalk. in fact, there are conditions where driving additional circuits in paral- lel in a given configuration can actually reduce the crosstalk. areas of crosstalk for a practical ad8110/ad8111 circuit, it is required that it be mounted to some sort of circuit board in order to connect it to power supplies and measurement equipment. great care has been taken to create a characterization board (also available as an evalu- ation board) that adds minimum crosstalk to the intrin s ic device. this, however, raises the issue that a systems crosstalk is a combination of the intrinsic crosstalk of the devices in addition to the circuit board to which they are mounted. it is important to try to separate these two areas of crosstalk when attempting to minimize its effect. in addition, crosstalk can occur among the inputs to a cross- point and among the outputs. it can also occur from input to output. techniques will be discussed for diagnosing which part of a system is contributing to crosstalk.
rev. a ad8110/ad8111 C19C measuring crosstalk crosstalk is measured by applying a signal to one or more channels and measuring the relative strength of that signal on a desired selected channel. the measurement is usually expressed as db down from the magnitude of the test signal. the crosstalk is expressed by: xt asel s atest s

20 10 log / where s = jw is the laplace transform variable, asel(s) is the amplitude of the crosstalk-induced signal in the selected channel and atest(s) is the amplitude of the test signal. it can be seen that crosstalk is a function of frequency, but not a function of the magnitude of the test signal (to first order). in addition, the crosstalk signal will have a phase relative to the test signal asso- ciated with it. a network analyzer is most commonly used to measure crosstalk over a frequency range of interest. it can provide both magni- tude and phase information about the crosstalk signal. as a crosspoint system or device grows larger, the number of theoretical crosstalk combinations and permutations can become extremely large. for example, in the case of the 16 8 matrix of the ad8110/ad8111, we can examine the number of crosstalk terms that can be considered for a single channel, say in00 input. in00 is programmed to connect to one of the ad8110/ad 8111 outputs where the measurement can be made. we can first measure the crosstalk terms associated with driving a test signal into each of the other 15 inputs one at a time. we can then measure the crosstalk terms associated with driving a parallel test signal into all 15 other inputs taken two at a time in all possible combinations; and then three at a time, etc., until, finally, there is only one way to drive a test signal into all 15 other inputs. each of these cases is legitimately different from the others and might yield a unique value depending on the resolution of the measurement system, but it is hardly practical to measure all these terms and then to specify them. in addition, this describes the crosstalk matrix for just one input channel. a similar crosstalk matrix can be proposed for every other input. in addition, if the possible combinations and permutations for connecting inputs to the other (not used for measurement) outputs are taken into consideration, the numbers rather quickly grow to astronomical proportions. if a larger crosspoint array of multiple ad8110/ad8111s is constructed, the numbers grow larger still. obviously, some subset of all these cases must be selected to be used as a guide for a practical measure of crosstalk. one common method is to measure all hostile crosstalk. sus term means that the crosstalk to the selected channel is measured, while all other system channels are driven in parallel. in general, this will yield the worst crosstalk number, but this is not always the case due to the vector nature of the crosstalk signal. other useful crosstalk measurements are those created by one nearest neighbor or by the two nearest neighbors on either side. these crosstalk measurements will generally be higher than those of more distant channels, so they can serve as a worst-case measure for any other one-channel or two-channel crosstalk measurements. input and output crosstalk the flexible programming capability of the ad8110/ad8111 can be used to diagnose whether crosstalk is occurring more on the input side or the output side. some examples are illustrative. a given input channel (in07 in the middle for this example) can be programmed to drive out03. the input to in07 is just terminated to ground (via 50 or 75 ) and no signal is applied. all the other inputs are driven in parallel with the same test signal (practically provided by a distribution amplifier), with all other outputs except out03 disabled. since grounded in07 is programmed to drive out03, there should be no signal present. any signal that is present can be attributed to the other 15 hostile input signals, because no other outputs are driven. (they are all disabled.) thus, this method measures the all-hostile input contribution to crosstalk into in07. of course, the method can be used for other input channels and combinations of hostile inputs. for output crosstalk measurement, a single input channel (in00 for example) is driven and all outputs other than a given output (in03 in the middle) are programmed to connect to in00. out03 is programmed to connect to in15 (far away from in00), which is terminated to ground. thus out03 should not have a signal present since it is listening to a quiet input. any signal measured at the out03 can be attributed to the output crosstalk of the other seven hostile outputs. again, this method can be modified to measure other channels and other crosspoint matrix combinations. effect of impedances on crosstalk the input side crosstalk can be influenced by the output impedance of the sources that drive the inputs. the lower the impedance of the drive source, the lower the magnitude of the crosstalk. the dominant crosstalk mechanism on the input side is capacitive coupling. the high impedance inputs do not have significant current flow to create magnetically induced crosstalk. however, significant current can flow through the input termi- nation resistors and the loops that drive them. thus, the pc board on the input side can contribute to magnetically coupled crosstalk. from a circuit standpoint, the input crosstalk mechanism looks like a capacitor coupling to a resistive load. for low frequencies the magnitude of the crosstalk will be given by: xt r c s sm
20 10 log where r s is the source resistance, c m is the mutual capacitance between the test signal circuit and the selected circuit, and s is the laplace transform variable. from the equation it can be observed that this crosstalk mechanism has a high-pass nature; it can also be minimized by reducing the coupling capacitance of the input circuits and lowering the output impedance of the drivers. if the input is driven from a 75 termi nated cable, the input crosstalk can be reduced by buffering this signal with a low output impedance buffer. on the output side, the crosstalk can be reduced by driving a lighter load. although the ad8110/ad8111 is specified with excellent differential gain and phase when driving a standard 150 video load, the crosstalk will be higher than the minimum obtainable due to the high output currents. these currents will induce crosstalk via the mutual inductance of the output pins and bond wires of the ad8110/ad8111.
rev. a ad8110/ad8111 C20C nnn5nnnn nnnnnnnnn nnnnn6nnn5n nnnnnng xt mxy s r l
20 10 log / where mxy is the mutual inductance of output x to output y, and r l is the load resistance on the measured output. this crosstalk mechanism can be minimized by keeping the mutual inductance low and increasing r l . the mutual inductance can be kept low by increasing the spacing of the conductors and minimizing their parallel length. pcb layout extreme care must be exercised to minimize additional crosstalk generated by the system circuit board(s). the areas that must be carefully detailed are grounding, shielding, signal routing, and supply bypassing. the packaging of the ad8110/ad8111 is designed to help keep the crosstalk to a minimum. each input is separated from each other input by an analog ground pin. all of these agnds should be directly connected to the ground plane of the circuit board. these ground pins provide shielding, low impedance return paths and physical separation for the inputs. all of these help to reduce crosstalk. each output is separated from its two neighboring outputs by an analog ground pin in addition to an analog supply pin of one polarity or the other. each of these analog supply pins provides power to the output stages of only the two nearest outputs. these supply pins and analog grounds provide shielding, physical separation and a low impedance supply for the outputs. individual bypassing of each of these supply pins with a 0.01 f chip capaci- tor directly to the ground plane minimizes high frequency output crosstalk via the mechanism of sharing common impedances. each output also has an on-chip compensation capacitor that is individually tied to the nearby analog ground pins agnd00 through agnd07. this technique reduces crosstalk by prevent- ing the currents that flow in these paths from sharing a common impedance on the ic and in the package pins. these agndxx signals should all be directly connected to the ground plane. the input and output signals will have minimum crosstalk if they are located between ground planes on layers above and below, and separated by ground in between. vias should be located as close to the ic as possible to carry the inputs and outputs to the inner layer. the only place the input and output signals surface is at the input termination resistors and the out- put series back termination resistors. these signals should also be separated, to the extent possible, as soon as they emerge from the ic package. evaluation board a four-layer evaluation board is available for the ad8110/ad8111. the exact same board and external components are used for each device. the only difference is the device itself, which offers a selection of a gain of unity or gain of two through the analog channels. this board has been carefully laid out and tested to demonstrate the specified high-speed performance of the device. figure 9 shows the schematic of the evaluation board. figure 10 shows the component side silk-screen. the layouts of the boards four layers are given in: component layerfigure 11 signal routing layerfigure 12 power layerfigure 13 bottom layerfigure 14 the evaluation board package includes the following: fully populated board with bnc-type connectors. windows based software for controlling the board from a pc via the printer port. custom cable to connect evaluation board to pc. disk containing gerber files of board layout. optimized for video applications, all signal inputs and outputs are terminated with 75 resistors. stripline techniques are used to achieve a characteristic impedance on the signal input and output lines also of 75 . figure 8 shows a cross-section of one of the input or output tracks along with the arrangement of the pcb layers. it should be noted that unused regions of the four layers are filled up with ground planes. as a result, the input and output traces, in addition to having controlled impedances, are well shielded. w = 0.008" (0.2mm) a = 0.008" (0.2mm) b = 0.024" (0.6mm) h = 0.011325" (0.288mm) t = 0.00135" (0.0343mm) top layer signal layer power layer bottom layer figure 8. cross section of input and output traces nnno9nnngn/0nnnkn6 nnnnnnnnn6n nnnnn/o5nnnnn/0nn nnnnnnnnnn6 nnnnnnnxnnn nnnnnnnn n nnn6 nnnnnnn
rev. a ad8110/ad8111 C21C 65 64 75 input 00 input 00 agnd 75 avee 41 40 0.01 f 39 67 66 75 input 01 input 01 agnd 69 68 75 input 02 input 02 agnd 71 70 75 input 03 input 03 agnd 73 72 75 input 04 input 04 agnd 75 74 75 input 05 input 05 agnd 77 76 75 input 06 input 06 agnd 78 75 input 07 input 07 2 1 75 input 08 input 08 agnd 4 3 75 input 09 input 09 agnd 6 5 75 input 10 input 10 agnd 8 7 75 input 11 input 11 agnd 10 9 75 input 12 input 12 agnd 12 11 75 input 13 input 13 agnd 14 13 75 input 14 input 14 agnd 16 15 75 input 15 input 15 agnd 59 data out 59 data in 80 dgnd p2-5 p2-4 p2-2 p2-3 p2-1 p2-6 reset dgnd ce clk update ser /par a0 a1 a2 d0 d1 d2 d3 d4 p2-5 p2-4 p2-2 p2-3 p2-1 p2-6 p2-5 p2-4 p2-2 p2-3 p2-1 p2-6 p2-5 p2-4 62 61 60 58 56 55 54 53 52 51 50 49 48 47 serial mode jump r25 20k dvcc 46 42 75 avcc 38 37 0.01 f 36 75 avee 35 34 0.01 f 33 75 avcc 32 31 0.01 f 30 75 avee 29 28 0.01 f 27 75 avcc 26 25 0.01 f 24 75 avee 23 22 0.01 f 21 75 20 agnd agnd output 00 avee agnd output 01 avcc agnd output 02 avee agnd output 03 avcc agnd output 04 avee agnd output 05 avcc agnd output 06 avee agnd output 07 avcc 19 0.01 f avcc avcc 18 0.01 f avcc avee 17 0.01 f avee 0.01 f 45 avee avee 0.01 f 44 avcc avcc 0.01 f 43 avcc avcc 0.01 f 63 dvcc 0.01 f 79 dvcc ad8110/ad8111 dvcc dgnd nc avee agnd avcc nc p1-1 cr1 cr2 + + + p1-2 p1-3 p1-4 p1-5 p1-6 p1-7 0.1 f10 f 0.1 f10 f 0.1 f10 f dvcc dvcc figure 9. evaluation board schematic
rev. a ad8110/ad8111 C22C figure 10. component side silkscreen figure 11. board layout (component side)
rev. a ad8110/ad8111 C23C figure 12. board layout (signal layer) figure 13. board layout (power plane)
rev. a ad8110/ad8111 C24C nnnnn5n5nnn nnnn5nn5n v cnn6n nn v cnnnnnnnnn5 nnnnnnnnnnnx nnnnnnn6 nnn5nnnnnsnnn nnmnnnnnnn767/n a 6nnnnnn5nnnnn nnnnnnnn 6nn76/n a n5nnnnnn5 nnnnnnnnnn6n n/7n a nnnnnnnnn nnnnn6 controlling the evaluation board from a pc the evaluation board includes windows-based control software and a custom cable that connects the boards digital interface to the printer port of the pc. the wiring of this cable is shown in figure 15. the software requires windows 3.1 or later to oper- ate. to install the software, insert the disk labeled disk #1 of 2'' in the pc and run the file called setup.exe. additional installation instructions will be given on-screen. before begin- ning installation, it is important to terminate any other windows applications that are running. when you launch the crosspoint control software, you will be asked to select the printer port you are using. most modern pcs have only one printer port, usually called lpt1. however some laptop computers use the prn port. reset clk data in dgnd ce update molex 0.100" center crimp terminal housing 1 6 d-sub 25 pin (male) 14 1 25 13 evaluation board pc 2 3 4 5 6 25 3 1 4 5 2 6 signal ce reset update data in clk dgnd molex terminal housing d-sub-25 figure 15. evaluation board-pc connection cable figure 14. board layout (bottom layer)
rev. a ad8110/ad8111 C25C n/0nnnnnnnnnn nnnsnnm6nnn5nn nnnnnnnnnn nnnnnnn/0n r nknxn6 nnnnnn5nnn nnnnn97xnnnnn 6nnnnnnnnnn nnnn6nnnnn5nnn reset overshoot on pc printer ports data lines the data lines on some printer ports have excessive overshoot. overshoot on the pin that is used as the serial clock (pin 6 on the d-sub-25 connector) can cause communication problems. this overshoot can be eliminated by connecting a capacitor from the clk line on the evaluation board to ground. a pad has been provided on the solder-side of the evaluation board to allow this capacitor to be soldered into place. depending upon the overshoot from the printer port, this capacitor may need to be as large as 0.01 f. figure 16. evaluation board control panel
rev. a ad8110/ad8111 C26C outline dimensions dimensions shown in inches and (mm). 80-lead plastic lqfp (st-80a) seating plane 0.063 (1.60) max 0.030 (0.75) 0.020 (0.50) 0.003 (0.08) max 0.057 (1.45) 0.053 (1.35) 0.006 (0.15) 0.002 (0.05) 0.011 (0.27) 0.007 (0.17) 0.559 (14.20) 0.543 (13.80) 0.476 (12.10) 0.469 (11.90) 0.476 (12.10) 0.469 (11.90) 0.559 (14.20) 0.543 (13.80) top view (pins down) 1 20 21 41 40 60 61 80 0.020 (0.50) bsc controlling dimensions are in millimeters
rev. a ad8110/ad8111 C27C revision history location page data sheet changed from rev. 0 to rev. a. universal change in nomenclature from mqfp to lqfp comment added to outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
rev. a C28C c01069C0C2/02(a) printed in u.s.a.

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